Not sure if this was mentioned already, but I could also only find the DAC0808 at my usual supplier (reichelt) and I found that someone successfully used the 808 instead of the 800 here
So I will go with that one as well 
I just noticed something in Sebastianâs version; thereâs a 1k series resistor, R39, between the output of BUFFER1F and the pulse output jack. This appears to have been added in this version and isnât present in Benâs. However, this resistor is upstream of jacks board R1 and the LED, which creates a voltage divider. Its effect will depend on the LED and it maybe doesnât matter much: I guess the BUFFER1F output level is about 9 V in which case a quick sim shows it being reduced to 7 V by the voltage divider, and as long as itâs above ~5 V itâs probably fine. But in principle the series resistor should be downstream of the connection to the LED and its resistor.
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Good find! Yeah, I added it to have the âusualâ 1k output protection. Moved it to the jack board now, directly in front of the output socket, should be good now
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Another thing I noticed, from Whitwellâs original design: The CV OUT goes through a 50k attenuator pot. Iâm not a great fan of output attenuators generally but I guess a case can be made for it here. But that means the output impedance varies between 1k and 51k. However, into a 100k load, itâs still very close to linear. Probably not worth worrying about, but the pot could be changed to say 5k if you really wanted to be obsessive about it.
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Looking again at the circuit⊠am I nuts, or is there a significant mistake here?
IC7B is wired as a comparator, powered with ±12 V. But that means its output is either +10.5 V or -10.5 V (more or less). And itâs being sent into the 4016 control pins, but those are supposed to be limited to voltages above 0.5 V⊠right?
And also, the control inputs on the 4016 are high impedance, so whatâs the series 100k resistor doing there? And why is a 4016 being used for what appears to be logic?
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I think you can pull the control pins up to Vcc to turn on the switch, right? 12V in this case.
Yes, the high voltage is fine. But it looks to me like the low voltage is 10 volts below absolute âmaximumâ (technically minimum, but whatever). That is, the good voltage range is -0.5 to 12.5 V, and this appears to be sending it -10.5 V.
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Hm, I have read some datasheets and the max and min voltage was usually only given for the input and output, not for control. in one only currents were mentioned, no voltages. So, this is probably running the chip out of spec, but apparently it still works. So maybe thatâs the also the reason for the 100k resistor (R4), to make sure the currents are low, so nothing can melt?
And yes, it is only used for logic, so it could be replaced by proper logic chips, but maybe that is less intuitive? You would need a few more logic gates to make this kind of switch, I guess, but probably you could replace the whole array of 4 switches with a few logic gatesâŠ
https://www.ti.com/lit/ds/symlink/cd4016b.pdf
I take âall inputsâ to include the controls â otherwise I would expect there to be a limit stated separately for the controls.
There canât be a current, right? The control inputs are very high impedance. Well, who knows what happens when the voltage is out of spec. But if I found my chips were failing if I didnât put a 100k resistor there I think Iâd look into the reason and realize the voltage needed to be dealt with.
Took me a while to puzzle out, but I think itâs just passing END_OF_LOOP if the output of the NOISE comparator is low, and inverting END_OF_LOOP if the comparator output is high â or in other words, itâs just doing an XOR. One gate.
The 100k resistor was used for the inverting transistor circuit in the original design. It may have just been left behind when the circuit was adjusted to use the two extra switches for the inverting. Or it could be a pull up resistor.
Switching to an XOR gate would require the addition of some more op amps to adjust voltage, right? With the switches, it just sends the End of Loop signal straight back in, or inverts it and sends it back in. Also, with the switch, the logic is happening outside of that signal. The logic would be in line with the signal with XOR. Am I thinking about this right?
I take the stance that if it isnât broken, donât fix it.
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I donât see why â END_OF_LOOP is a 4015 output, 0 V or 12 V, that can go into the XOR. The comparator output then should have a diode+resistor to condition the low level, but in principle it should have that for the 4016.
Not sure what youâre getting at, so I donât knowâŠ
Thereâs something to that. But if itâs 10 V out of spec I have trouble leaving that alone.
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In the case the CV threshold is below the noise, the noise randomly turns the switch on or off, sending either end of loop or inverted end of loop. When the CV is over the threshold, it always sends the end of loop.
With XOR, when the CV threshold is below the noise, the randomness of the noise still send random values, so the result will still be random (though the state of the end of loop has impact on it this way). When the CV threshold is below the noise it will send high or low depending on the end of loop value.
Do we get the same results with the CV threshold all the way up? It flips every bit in the existing version. With XOR it would flip the highs and keep the lows, filling the mobius strip of switch version up with all lows.
With the Turing machine, we need to be able to hold high all of the time (send end of loop through), hold low all of the time (invert end of loop), or vary the randomness (full random in this case is flipping 50% and keeping 50%). A single XOR gate would not allow this. You can probably figure out a way with more logic, but that would likely add more ICs to the project.
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The noise is randomly determining when to flip the end of loop. In locked state (5pm), the threshold value will be above all noise values, so end of loop is never flipped. In full random mode (12pm), the noise will be above the threshold value approximately 50% of the time, flipping approximately 50% of the bits. In mobius strip mode (7pm) the threshold value will always be below all noise values, flipping all end of loop values.
If I am thinking correctly, and I may very well not be, the XOR can be set up to act about the same for the 12pm to 5pm values, but would not work for the 7pm setting. It could also be set up to work for the 12pm to 7pm values, but would not work for 5pm, but that would be even less desirable. You would have 4 XOR gates in the 4030 that would likely be the IC used here. Maybe you could figure out how to use them to make both ways work. Even if you did get there, you would be at the same part count as the current implementation.
This forced me to understand the Turing Machine better than I did while I was designing the board.
I may not have a full understanding of the proposed XOR solution.
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My analysis is:
If the comparator output is high, then SWITCH_IC1A and SWITCH_IC1D are closed. Then END_OF_LOOP (which is just the bit value, high or low, in the shift register position selected by the rotary switch) is sent to START_OF_LOOP to be written into the shift register; the shift register pattern does not change. Meanwhile the C input on SWITCH_IC1B is driven low, so that switch is open and doesnât affect START_OF_LOOP.
If the comparator output is low, then SWITCH_IC1A and SWITCH_IC1D are open. The former then doesnât affect START_OF_LOOP. SWITCH_IC1C drives input A of SWITCH_IC1B low if END_OF_LOOP is high, otherwise that input is high, and the control input of SWITCH_IC1B is high, so the inverse of END_OF_LOOP is sent to START_OF_LOOP.
In summary, if the comparator output is high, END_OF_LOOP is sent to START_OF_LOOP, and if the comparator output is low, END_OF_LOOP is inverted and that is sent to START_OF_LOOP. This actually is the opposite of what I originally thought, which was that comparator high inverted and comparator low did not invert.
The only randomness is whether the comparator output is high or low â nothing after the comparator is random.
LOOP_CTRL is inverted by IC1A so the comparator threshold is high when at 7pm and low at 5pm. In the former case the noise is always below threshold, so the comparator is always low and the bit is always flipped. In the latter case the noise is always above threshold, the comparator is high and the bit is never flipped. At noon the comparator is high half the time and the bit is flipped at random.
The logic table is:
| END_OF_LOOP | COMPARATOR | START_OF_LOOP |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
which is NOT XOR. And is not XOR⊠but I think it could be reproduced by reversing the inputs on the comparator and using an XOR. I claim that would work the same: the comparator outputs would be inverted compared to what they are now, and then XOR of that with END_OF_LOOP would always flip bits at 7pm and never flip them at 5pm.
But in the end, while I think it could have been simpler, the design works as it is and might as well be left alone, as far as the logic is concerned. I do think, though, that replacing the series resistor with a diode and pulldown resistor to keep the voltage on the control pins above -0.5 V would be a good thing to do.
Yes, it does seem that XNOR may work. At least it fixes the problem I saw with the XOR. If one was feeling ambitious, they could redesign the circuit around that and try it out. I am not so ambitious. I have a circuit that works.
I saw where Tom mentioned lowering the operation voltage in the switching circuit between the two versions, but I am not sure what he meant by that.
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Maybe this is the answer to my voltage objection. From the TI CD4016 datasheet:
This seems to have protection diodes on the control inputs clamping it to the -0.5 to VDD+0.5 range. If connected directly to the op amp output it would still be a problem, but with a series resistor, it can drop the negative voltage across the resistor and limit current through the diodes. Itâs not how Iâd design it but I suppose it works and is technically within spec since the voltage on the pin doesnât exceed -0.5 V.
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Did the DAC08CPZ work?
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Yes. Seems to work fine.
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The 100K resistor is indeed what is preventing the circuit from frying, but relying on the protection diodes is not good design practice.
The spec says to keep the input voltage above -0.5V so that the protection diodes do NOT conduct.
At worse, an external Schottky diode to ground should be added.
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Technically (says the devilâs advocate) the datasheet does not say the diodes must not conduct; all it says is the pin has to be kept above -0.5 V â and it will be, provided thereâs a series resistor (and the internal diodes have low enough forward voltage).
Still, this design doesnât please me. But itâs been in use for years and so far as I know it works.
That will indeed keep the internal diodes from conducting⊠if its forward voltage is lower than that of the internal diodes. If itâs higher then the current will flow through the internal diodes and not the external one. I donât see anything in the datasheet that tells what the internal diodesâ forward voltage is, though. They do use a regular junction diode symbol, not Schottky, in the schematic diagram, so maybe itâs on the high side.
Added next morning:
Found this:
and
~10.5V V through a 100k resistor is only ~105 ”A, far below that 10 mA, so the protection circuit really isnât at risk. Still, it looks like indeed a Schottky diode with Vf ~ 0.2 or 0.3 V will take that 105 ”A out of the picture. So why not? âIf it ainât broke donât fix itâ â except when the fix is as trivial as this.
It so happened earlier yesterday Iâd uploaded the Halting Problem design to JLCPCB â but Iâd held off on checking out the order, to give myself time to give it a last think-over. So now I have a different version uploaded, one with a Schottky footprint added.
(I still havenât checked out the order, someone can still talk me out of it. Or of course I can just leave that footprint empty if I change my mind.)