I open a hex inverter thingy from a friend that i would like to have a schematic for it… im very bad at that but i could put a DIYLC layout on order to make it easier than showing fotos of the whole mess from that thing
Is there some schematic hero who can help out with the task?
2 output jacks… One chip,few caps and resistors and many pots… And basically one half of the chip is the main circuit, the 2nd half is just the same
Hello, could you please give us more information about this circuit and what it is you need ? Also, I may be wrong but I don’t see any power supply on the schematic you provided (pin 7 is GND and pin 14 is Vdd on the cd40106)
Okay, I THINK this is correct, but I haven’t done any checks on it or anything. I did find one error in your layout, which was that D6 was connected to pin 9 on the 40106, and I think it was supposed to be pin 8. I numbered the pots RVn, where n is the same number as the diodes and caps it’s connected to. RV11 is the power attenuator. I kept all the other identifiers the same. There’s no component values, since there were none on your schematic. Hope this helps!
Woaaah!! That was insanely quick!
Thank you very very much…
I think i saw that oin 7 is not grounded as per in layout… but i can work with it and re check everything slowly… Also. I’ll check tomorrow at home, if that connection you pointed out on my layout, is wrong… thanks a lot again !
My attempt is somewhat different. I used separate symbols for each of the Schmidt triggers to make it clearer what’s going on — EasyEDA’s tendency to use a single uninformative rectangle for an IC I think is one of its biggest problems. The output stages for the two sides should be the same (and I think they’re reversed above, but it doesn’t matter), and it looks like some ground connections were missed.
But the output section doesn’t really make much sense to me. Why the two resistors in parallel? What are C9/C12 doing? My guess is the wires from the stripboard to C9/C12 are connected to the wrong ends of those capacitors, and it should be like this:
and then R1 is a pulldown and C9/R4 and R3/C7 are a (fixed) high pass filter and a (fixed) low pass filter which can be mixed in or out with RV7 — so a tone control, and C8/RV8 are a variable high pass filter.
(By the way, above schematic should be labeled “Unverified”, as should the stripboard layout assuming no one here has built it:)
Also, I’ve read that if you try to use all 6 Schmidt triggers in a 40106 for oscillators, you may get crosstalk between them. If you care about that.
Yeah, my plan was to do it that way, but I ended up with time to do it at work today and all I had access to was the online version of EasyEDA. Separate symbols for each inverter would have made my schematic a lot more readable!
I have heard that as well, but since this is a noise circuit I doubt that’s going to be a huge concern.
I’ll stamp my schematic as unverified when I have a minute to get in front of my computer tonight.
I can confirm this from experience, particularly when using a breadbooard, wherein there is probably cross coupling between adjacent strips, also via ground given that breadboard power buses can be relatively high resistance. Ive had similar issues with oscillators built around the 4093 Schmitt Nand gates.
But as you said it’s a noise synth and arguably this phenomenon could add character to the synth.
Thanks a lot for the effort and the time to do this, really appreciate it… I check that i had wrong connected D6 in my first layout ( it should have been connected to pin 8)
Also a mistake in R3-C9 and for instance R5-C12
(Please check the updated layout )
I updated here the updated layout, as well with more infos and the unverified mark
And extra photos for the tone pot wiring
Thanks again for the help, time and effort in order to help me out on this one
This is more a tendency by its users who define their own symbols in my experience, not so much an EasyEDA habbit. But I agree that it is much easier to understand a schematic if it is composed of electrical symbols in stead of being defined by an IC’s topograpy.