My "4066" VC Envelope Generator

[rodrigoDMH]

Finally, the Dual VCEG build is complete and (mostly) working!

The base circuit is inspired by the MFOS ADSR, which I expanded with voltage control for all parameters, LEDs, inverted output, sustain gate output, “release only” output (which doesn’t work…), super fast mode, and ADR looping. All CV inputs have their own attenuverter.

Demo: https://youtu.be/IbwRrnVJeVw?si=PNbH8NBv8-50m8Ea

Git: GitHub - DeMarco/DMH-VCEG

This freaking module gave me so much work to design and test that I’m really looking forward to an easier project next…

Unfortunately I still need to redesign one of the PCBs with an improved solution for the “release only” auxiliary envelope (inspired by the Moog Grandmother VCA’s “keyboard release” mode). For some reason it works perfectly on the breadboard, but the BS170 MOSFETs I used keep going bad on the PCB. I’ll just do away with them entirely and use one more CD4066E instead. With that, the module will count 26 ICs and exactly 200 resistors (plus all the rest), so that gives a hint on how much of pain in the butt it was to build. I never thought a VC envelope would be such a “non trivial” thing to make.

When the new PCB version is ready I’ll inform it here. Will also write a procedure on how to calibrate the thing if anyone is interested.

[krztoff]

I absolutely love it. Fine work!

[krztoff]

Does this by chance have the ability to trigger on end-of-cycle? Since it’s looping, I assume that a trigger is generated somehow and I could theoretically tap into that?

[rodrigoDMH]

I think you could tap into that, yes… there is no space for a jack to expose that trigger to the outside world, but you could solder a wire to the back and expose that signal via another module. I need to check exactly where in the PCB you could tap, will let you know this evening.

Alternatively, the Sustain Gate Out goes low when the EG enters the Release stage. You could use a module with Falling Edge detection to trigger on that, but of course this would not be the true “end of cycle” moment, unless your Release setting is set to minimum.

[rodrigoDMH]

So, you can use the net highlighted in purple as an “end of cycle” gate output. It’s just a comparator that goes high (around 10V) if the EG output drops below 25mV, which means the Release phase has finished. When the EG output goes above 25mV, you’ll get GND via the 10k resistor.

Just solder a wire to either of these 3 terminals on the main PCB.

[krztoff]

that’s awesome. thank you!