Can Someone Look at My Buffered Mult Schematic Please?

[fredrik]

@analogoutput

Then output = input voltage regardless of what load you connect. (There can be drawbacks to doing it this way so some like to use it only when preserving V/oct CV is needed.)

The “in-the-loop” pattern is often used to deal with capacitive loads:

Output stage topologies

I have an application note that discusses this somewhere but cannot find it right now, but iirc the version with the output resistor in the loop can deal with capacitive loads (e.g. long patch cables) a bit better. (the resistor itself is also there to protect the output stage and more importantly protect other modules, by limiting the current in and out of this module.)

What are the drawbacks, besides using one more (optional) capacitor? (if you’re aware of any specific ones, post them in the linked thread )