My postman sent a message saying that my Plexquencer will arrive tomorrow. Where can I find the BOM? Or better: which weekend?
Iâm considering buying one, but I want more information first.
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You donât realy need a BoM , itâs all on the board bar a 100nf cap.
Allong the lines of
Some 1n4148âs
TL074
CD4051 i think
CD4081 i think
100K pots
10uf Lectrolitics
100nf caps
100k, 1m, 1k resistors
eurorack header
spdt switches
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Well not sure how itâs supposed to work, but it does not seem to do anythingâŚ
Await the schematic and description of operation before trouble shooting 
thanks, i will give it a try tomorrow.
BOM and schematic are up.
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In A, B, C are the binary address pins of the 4051. They control which of the outputs In V gets routed to. So if A, B and C are all low (binary 0), In V gets routed to Step 1, if A is high and B and C are low (binary 1), In V gets routed to Step 2 and so on.
At this point the signal is separated for CV and Gate processing. The pot associated with that step attenuates the signal, and routes it to CV Out. The switch associated with that step routes the signal to one of two gate buses. When a gate is received on In G, it is logically ANDed with the signals present on Bus 1 and 2, and the result is sent to Gate Out 1 or 2 (bottom two jacks).
To test whether your build is working, you could do something like this:
- Send a steady +10V to In V (doesnât need to be precise â as long as itâs more than 8.4V and less than 12V).
- Send a clock to In G. High level must be at least 8.4V
- Set Switch 1 to the left (Gate Bus 1).
This should give you a gate out on OV+1 whenever the clock is high, and a CV signal that you can vary between 0-10V on OV+V. If this is not happening for you, check that your clock is putting out a sufficiently high voltage. These are CMOS logic chips, so a logical high is over 70% of the supply voltage.
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Anyone understand why thereâs a 1k/1M voltage divider on each input? (Not 1m, that would be one milliohmâŚ)
Iâm very surprised the logic inputs use voltage followers instead of comparators (or transistor buffers), which would allow use of much lower gate voltages. 8.4 V is a pretty stiff gate requirement.
Perhaps the thinking was to keep the logic modules happy by ensuring that logic high will never exceed the supply voltage? Just guessing. Doesnât really make sense as the op amps will be saturating by then in any case, but I canât think of another explanation.
Yes, especially given that it is ANDed with the In V. Means that you wonât get a gate output unless both the gate and the input voltage are above 8.4V. Unless Iâve misunderstood something.
Not quite getting what this means:
Voltage input, this overtakes the stationary voltage fgoing into the multiplexer, which then can make it act as either a scaled output of the input, or you can use it to send an lfo to either the voltage output or either of the gate outputs, meaning it is a 3 output distributor.
This sounded to me like it meant the voltage input affects not only the scale of the CV output but the amplitudes of the gate outputs too. But the gate outputs are the result of ANDing the 4051 output with the gate input, and the AND chip is powered with +12 V, so theyâll be +12 V outputs regardless of what the voltage input is. Unless the voltage input is below +8.4 V, then there wonât be any gate outputs⌠I think.
But maybe itâs supposed to mean something else and Iâm just not understanding.
so how is it supposed to work, I have gate in, but the sequence does not run?
Have you tried what I suggested earlier?
Order is in ⌠but Iâm thinking about a mod to lower the gate voltage requirement.
in the test equipment video of the sequencer that sam says this was inspired by he also uses some sort of voltage divider (?) that he built into his vco. he plugs the divisions into the a/b/c inputs. so, what should we plug in if we donât have such a divider?
this is the video:
Itâs a clock divider. Just feed it clocks, gates, any kind of pulse wave that can serve as a logic input. This is the truth table:
If you wanted it to count from 1-8 (actually 0-7) sequentially, like an ordinary sequencer, you would feed In A Clock/1, In B Clock/2, and In C Clock/4. Notice how that lines up with the zeroes and ones in the relevant columns of the truth table. If you wanted it to do something more interesting, you could feed each input pulse wave LFOs (like from the hex oscillator box that Sam builds in that video). That would settle into a more interesting sequence, which you could scramble by changing the frequency of the LFOs. If you google Lunetta Binary Sequencer, youâll find a lot of variations on this theme. Thereâs even a VCV library that you could experiment with to get the idea: VCV Library
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thanks! ok @lookmumnocomputer please provide stripboard layout for your vco/clock divider 
As noted here:
https://electro-music.com/forum/post-434679.html#434679
Added: Wait, look what @EddyBergman just posted today!
This seems to use a 5 V regulator to power the 4017, which means the divided clock pulses will be 5 V amplitude. As noted above, that wonât work with the Plexquencer. Youâd have to substitute a 9 V regulator, or just skip that and use the +12 V rail.
The YuSynth divider provides 10 V outputs (or 5 V if you add the Zeners, not included in the stripboard layout).
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Oof, looks like the same will be true with Lattice/Grids [ Index - Mutable Instruments Documentation ], which I was hoping to pair in gate mode as a rhythmic arpeggiator.
LOL, thatâs a coincidence 
Looks like I timed it well
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Mine uses a CD4024 and you can choose the voltage you want to power it with by altering the type of voltage regulator you put in. Mine is running on 8V.
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