The current limiting resistor on the output doesn’t need to be 100k. There may have been a need for such a high value in Klein’s sample and hold but if this is for an output jack, 1k would be the more normally used value. 100k might work, but if the downstream module has a typical 100k input resistance, it’ll result in a factor of 2 reduction in the voltage.
It’s good practice to add bypass capacitors. 100 nF ceramics from the chip power pins (4 and 11) to ground, placed as close as conveniently possible to the pins, and 10 µF electrolytics from the ±12 V rails to ground near where they connect to the board.
In DIYLC you can reduce the opacity of the chip to make the trace cuts visible.
Some simplifications to your layout are possible. There is a jumper from row E to row I and a resistor from row I to row H. You could just put the resistor from row E to row H and omit the jumper. Similarly instead of the jumper from row F to row J, you could move the resistor and green wire to row F.
The blue jumper not only should go to pin 11 but should come from the bottom row.
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