How to build Doubler Tempo / Problem DIY synch Arturia/EKO Panda

Hello everybody.

(Sorry for my english, I’m french).
Since spring 2019, I build my modular. Thank you a lot everybody for sharing schematics, topics etc.

I would like some help to build an electronic part to synchronise my KeyStep (or Beat step Pro) with my keybord EKO PANDA61 '1981 Keybord.
If it’s possible, I prefer do an electronic passive building.

I had creat a ‘Jack INPUT SYNC CLOCK’ on the Panda keyboard (direct link on Pot Tempo / open circuit on Jack). Hot point pot tempo on the keybord can be receive.
When I link ‘CLOCK OUT’ on BS/Keystep to Building ‘JACK SYNC IN Panda’ it works.
But, for exemple, if the BSP/KeyStep is on 120bpm, the Eko keyboard is on 60bpm. (Tempo SYNCH IN Panda = 1/2 tempo Arturia).

I researsh to build a tempo doubler or create a positive trigger on falling edge on clock…

Thanks a lot.

Amicalement.
Jim

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There’s a recent discussion of a clock multiplier here which might work although it’d be massive overkill for your situation.

I’d think one could use an RC to differentiate the clock, rectify both that and its inverse (from an op amp inverter) and combine the two to get triggers on both edges, but I can’t point to a polished design…

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Another option would be to make an external clock source with a divider that divides the frequency by 2 (this can be done with a simple flipflop). Connect the Eko keyboard to the external clock directly and the BSP to the divider. In this way the Eko gets twice the clock frequency as the BSP and both run at the same speed.

Also, you could try to get hold of a service manual of the Eko and see what causes the division of the clock signal. Maybe that circuit can be bypassed.

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Hi, thanks a lot.
I thought well to make that with an Arduino. But i prefer a easy build with chips.

Hi, thanks Jos. But I preder keep the original tempo on BSP.

If you really want to build it with chips, this is how I’d do it.
Start with a CD4046 - it’s a phase locked loop.

image

In the divide by N box between pins 3 and 4 of the PLL you’d put a flip-flop to divide by 2. Connect the inverted Q output to the D pin. Connect the clock to pin 4 of the PLL and Q (or inverted Q depending on the phase you wanted) to pin 3 of the PLL. Depending on the selection of components for the low pass filter, you should quite quickly get a relatively stable 2x clock on pin 4 that you can buffer and use.

You could get creative and put selectable divider circuits between pins 3 and 4 of the PLL so you could get different multiples of the input frequency if so desired.

I’ve done something similar to create a sub osc that can do down an octave, up a fifth and up and octave. Hit me up if you want more details.

Cheers

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