Okay, I think I get the idea of this. I’ve been working with a simulation of the Haillant LFO core with this sync:
tl;dr: This should work, but for best results you need to adjust component values so R33*C31 >> R36*C1, and Vss(R37/R36) equals the triangle wave peak voltage. If you are switching values for C1, as in the Haillant LFO, you may need to also switch values for C31 simultaneously.
The idea is this (references are to the above sync diagram, they’re different in the simulation). C31 and R33 differentiate the input sync signal to make short positive and negative pulses, as shown; IC3a acts as a comparator and the diode and +V at R34 give a short negative going pulse, which turns off the gate on Q1 allowing it to conduct. RC is 100 µs so the gate pulse is about that long, actually closer to 150 µs.
Then what you have with IC1b, R37, and R36 is an inverting amplifier with input +V and gain 3.3k/6.8k, so the output will be about -6 V.
Of course it doesn’t change to -6V immediately, C1 has to charge through R36. RC here (for the LFO in the Magic Smoke diagram) is 6.8 µs, so it takes a few times that long to get there.
Now in the Haillant LFO the capacitor is either 10 nF or 1 µF instead of 1 nF. So in the 10 nF case the charging time constant is 68 µs. That’s long enough that the capacitor doesn’t fully charge in the time the gate is open:
The orange line is the incoming sync signal, the brown line is the gate voltage pulse, and the blue line is the triangle wave output. You can see the output is still dropping when the gate ends, and then it rises from there. To make the cap charge fully during the gate I cut R36 and R37 to 680 and 330 ohms, giving a charging time constant of 6.8 µs again:
The cap charges to -(330/680)*12 V = -5.8 V. However in this design the triangle wave starts at about -7.6 V, so what you see happening is it goes down from -5.8 V to -7.6 V before starting up again. So I changed R37 to 430 ohms, because -(430/680)*12 V = 7.6 V. Then it works as intended:
Here it is over a longer time period with several sync pulses:
All of which looks fine.
What’s problematic is when you switch the LFO range. Then you have a 1 µF cap and the charging time constant is 100 times longer, 680 µs with the smaller resistors. I don’t think you’d want to drop those resistors to 6.8 ohms and 4.3 ohms, so the alternative would be to lengthen the gate pulse by increasing C31 and/or R33. Say make C31 1 nF. Then there’s a delay of about 15 ms between the leading edge of the sync trigger and the start of the new triangle wave, which might be too long for the higher LFO rates. You’d maybe need to use a DPDT switch to change both C31 and C1 between small and large values.
Or at least I think so! There’s probably details I’ve overlooked.