Adding sync to an LFO

So I started off with the David Hillant LFO design:

I have it working on my breadboard. Now I would like to add this:

Apparently I cant just plug this setup in to the existing circuit (I tried). I imagine because the resistors are the wrong value. Any ideas on how I might get this to work?


I don’t understand this fully but if Q1 is conducting you’re charging C1 through R36. RC is 7 µs in Parkhurst’s diagram, so it should charge very fast. More to the point, R36 is much smaller than their R6 which presumably governs the period of the LFO, so charging time is much less than the LFO period.

You have larger capacitor(s) and smaller resistors in yours, but the resistance R1+R3 is 100k to 200k, which is still a lot larger than 6.8k. So again the charging time should be much less than the LFO period.

If it works in the one case I don’t see why it wouldn’t work in the other. You’ve verified the Q1 gate voltage is being pulsed correctly by the Sync In signal?

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Okay, I think I get the idea of this. I’ve been working with a simulation of the Haillant LFO core with this sync:

tl;dr: This should work, but for best results you need to adjust component values so R33*C31 >> R36*C1, and Vss(R37/R36) equals the triangle wave peak voltage. If you are switching values for C1, as in the Haillant LFO, you may need to also switch values for C31 simultaneously.

The idea is this (references are to the above sync diagram, they’re different in the simulation). C31 and R33 differentiate the input sync signal to make short positive and negative pulses, as shown; IC3a acts as a comparator and the diode and +V at R34 give a short negative going pulse, which turns off the gate on Q1 allowing it to conduct. RC is 100 µs so the gate pulse is about that long, actually closer to 150 µs.

Then what you have with IC1b, R37, and R36 is an inverting amplifier with input +V and gain 3.3k/6.8k, so the output will be about -6 V.

Of course it doesn’t change to -6V immediately, C1 has to charge through R36. RC here (for the LFO in the Magic Smoke diagram) is 6.8 µs, so it takes a few times that long to get there.

Now in the Haillant LFO the capacitor is either 10 nF or 1 µF instead of 1 nF. So in the 10 nF case the charging time constant is 68 µs. That’s long enough that the capacitor doesn’t fully charge in the time the gate is open:

The orange line is the incoming sync signal, the brown line is the gate voltage pulse, and the blue line is the triangle wave output. You can see the output is still dropping when the gate ends, and then it rises from there. To make the cap charge fully during the gate I cut R36 and R37 to 680 and 330 ohms, giving a charging time constant of 6.8 µs again:

The cap charges to -(330/680)*12 V = -5.8 V. However in this design the triangle wave starts at about -7.6 V, so what you see happening is it goes down from -5.8 V to -7.6 V before starting up again. So I changed R37 to 430 ohms, because -(430/680)*12 V = 7.6 V. Then it works as intended:

Here it is over a longer time period with several sync pulses:

All of which looks fine.

What’s problematic is when you switch the LFO range. Then you have a 1 µF cap and the charging time constant is 100 times longer, 680 µs with the smaller resistors. I don’t think you’d want to drop those resistors to 6.8 ohms and 4.3 ohms, so the alternative would be to lengthen the gate pulse by increasing C31 and/or R33. Say make C31 1 nF. Then there’s a delay of about 15 ms between the leading edge of the sync trigger and the start of the new triangle wave, which might be too long for the higher LFO rates. You’d maybe need to use a DPDT switch to change both C31 and C1 between small and large values.

Or at least I think so! There’s probably details I’ve overlooked.


Wow, thanks for all the leg work here. I have not had a chance to tinker on anything in the last few days - work has been keeping me busy. This, the clock divider, and my multi are currently occupying my mind space.

At this point I think I might just have to bite the bullet and find an oscillator see what is going on inside my circuits. Maybe that will help me visualize things better. I’ll report back when I get a chance to poke at it a bit.

Purely selfish motives, I’m building an MFOS LFO and want to try adding sync to that.


Rising tide floats all ships!

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(Level not quite calibrated but we’re getting there.)

Added: This uses a J112, with 680R and 330R (the MFOS LFO has 20 nF in the feedback). What does NOT work is: “If you want the triangle wave to reset to +V instead, connect R36 to -V”. Do drain and source need to be interchanged too? I thought drain and source were symmetric in most JFETs but maybe not the J112? Doing this does have an effect, but the effect is to shut down the oscillator, independent of the JFET state.


I have the feeling I’m going to need to pick up an oscilloscope. I have a real problem visualizing the way a transistor effects a circuit.

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this series of video is very well done with a comparison with water very easy to understand
maybe the last one for power supply

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My transistor understanding is pretty limited too. In this case the JFET is acting as a switch. Source connects to drain if there’s no voltage on the base. Apply a (negative, for N-channel JFET) voltage to the base and it turns the switch off. Kind of like stepping on a water hose.

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I was thinking maybe the reset to +V might need another JFET on the other side of the capacitor, but I didn’t have any more J112s; I did find some J113s, though. So I got a couple out and swapped one in for the J112, and before doing anything else I tested again, and this time the reset to +V worked!

I have no idea why the J112 didn’t work and the J113 did. From the datasheet the J113 has a smaller min and max gate-source cutoff voltage (but the ranges overlap), smaller min zero-gate voltage drain current, and larger max drain-source on resistance. Given that with the J112 the oscillator didn’t work even if no sync triggers were applied, I’d think the Vgs(off) is the relevant parameter — and since their ranges are fairly wide and overlapping, it might not be a J112 vs J113 thing but just a matter of individual JFET characteristics. Which further suggests the real problem is the gate signal it’s being sent. Hmm.


So the TL01 IC’s are required since they have the offset where as the TL02 and TL04’s do not?

Not sure what you’re referring to, but the only difference in the TL07x is the number of op amps in a package. I used a TL071 for this because only one op amp is needed.

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The TL071 has provision to adjust the output offset to null.
But I have never read that part of the datasheet in detail…

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I think I am about these:

Wouldnt we need more pins on the IC? Or are they just going to the existing + and -?

To me these look like the regular power supply pins.
Not the offset adjust ones.

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Oh yeah, that’s right. But I’m not using that.

Yeah, in the simulation I’m using the amp with power supply pins. Otherwise the comparator simulation gives you answers in gigavolts or something.

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Oh duh. Of course that is what they are. I forget, the Tl074 only has one set of power inputs for the four amps.

Anyway, Circuitlab doesn’t have TL074. It has TL081 and TL082 but they’re identical — so far as I can tell, there’s no provision for specifying two op amps are part of the same package. And there’s TL071, but no TL072 or TL074. And the offset pins for the TL071 don’t appear to be implemented.

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I ended up trying five different J113s, all from the same order so likely from the same manufacturing batch, and all worked.

After getting some more J112s I tried four of them, all from the same order, in addition to the one I’d tried from a different order, and none of them worked. I also tried one J111 and it didn’t work.

And I tried five 2N5458s, all from the same order, and they all worked.