Hey everyone!
I’d like to get your input on this module idea I have. Would it work in general? If yes, how could it be improved? If not, is there another (better) way to make something like this work?
A while ago I noticed, that a lot of my modules create trigger signals, which often stay unused. I wondered how I could utilize those triggers for rhythmic modulation purposes and proceeded to build myself a couple of simple decay envelopes. The following idea (inspired by the Traffic module by Jasmine & Olive Trees) is way cooler I think:
The module is supposed to take three trigger signals and turn them into adjustable control voltages. The voltage is then hold until another trigger signal is received. In case the module receives multiple triggers at once, there is a hierarchical order in place, which ensures, that Trigger 1 takes priority over the other two, while Trigger 2 also takes priority over Trigger 3.
Here’s what I came up with: A CD4051 Multiplexer acts as a switch for the three control voltages, while also establishing said hierarchy. The output of the CD4051 then goes into the signal input of a simple S&H circuit, which is triggered by all three trigger inputs.
I’m a total noob when it comes to logic IC’s so I would really appreciate your input!
I think that would work. Delay of CD4051 seems to be in hunders of nanoseconds, so even short trigger signals should work. I’d add a pull-down resistor to left side of capacitor C1 too. Maybe that unused op-amp could be used to make a inverted output or output of mix of trigger signals?
Thanks for your feedback! The pull-down resistor is a good call. I’ll certainly find a good use for the spare opamp if it turns out I don’t need it for something more crucial. A mix-output for the trigger signals has crossed my mind before. I might even add some more functionality after (and if) I get the basics working.
Today I’ve ordered the CD4051 and the JFET, so I can give it a try on breadboard
This would appseluttly work … I think.
Also I think I’ve seen something similar at Barton Musical Circuits, Yu-synth and Elby-Design (CGS).
Keep us posted.
My only concern is that if the triggers are far apart in time, the analogue sample and hold will eventually start drifting.
I would have latched the inputs on the digital side (no drift there), maybe with three D flip-flops clocked by the diode-ORed inputs. Then you don’t need the analogue sample and hold circuit at all.
Other possible improvement, add an offset to the output to allow for negative outputs.
Edit: I like how you used the analogue multiplexer as a priority encoder, very clever.
You should have some kind of input conditioning for the signals going into the 4051. As the circuit is now, the chip will get fried if an input is ever connected to -12V. Also when powered from +12V the 4051 needs like 8V to register a logic high, so if you have modules that output 5V or 3V gates they won’t work.
Lowering the supply voltage to 5 V as @Sandelinos suggested to make interfacing easier is a good idea. You can then add some diodes from gnd to the inputs and from the inputs to +V to prevent anything over +V or below gnd to reach the CD4051. Make sure to add a series resistor between every input and the diodes to limit the current just in case a signal that is too high or too low is applied. The value of the series resistor should not be too high so that the address lines of de 4051 can operate normally and not too low so that it case of over or under voltage it will overload the source of the under or over voltage. A few kOhm should be ok.
@antoine.pasde2 's idea of using D-FFs is a nice way to simplify the circuit without losing any functionality.
If the input conditioning is transistors or single supply op amps* powered by +12 V, then you can set a low threshold for the input gates and they’ll be converted to +10.5 V or higher, so you don’t need a 5 V supply for the 4051 (or the flip flops if you do that, which I would). And from the datasheet I think the analog inputs also have to be in the 0 to Vcc range, so with a 5 V supply you’d be limited to 0 to 5 V CVs.
Thanks for your input everyone! I’ve been constantly sick for the last two weeks, so I couldn’t follow up on this. Today I found the motivation and energy to test the basic circuit (as shown in the schematic) on breadboard and can confirm it works in principal (when using beefy triggers). Behaves a little wonky, though this might be caused by my shitty breadboards.
I found the drifting to be acceptable for most applications but of course if there is a way to get rid of it entirely I would like to explore that. Could you elaborate on your flip-flop suggestion, maybe even provide a schematic sketch? I read up on them, but I can’t quite wrap my head around how they would be implemented here..
Edit: I think I got it. Will upload a new schematic tommorow.
This is a nice idea. I wasn’t sure whether I wanted the module to output unipolar or bipolar voltages. The ideal solution would be the option to switch between those two modes and I think an offset to the output would be the best way to implement this.
Thanks for pointing this out! I will probably use opamp based comparators to amplify and unify the incoming triggers. Lowering the supply voltage would (as @analogoutput pointed out) also limit the accepted voltage at the channel in-/outputs (Vdd+0.5V according to the datasheet).
I reckon this would not be necessary if there is an opamp comparator between the trigger-inputs and the control inputs of the 4051? The opamp would of course have to be single supply or I’d use a diode and a pull-down resistor to block the negative voltage while the comparator is in its low state.
So this is the next version I’m going to test before adding more features. For the D flip-flops I chose the CD4076B, because it contains four of them with a common clock input and is suitable for +12V voltage supply and signal levels.
If there is an input signal connected to the jacks that may exceed the supply voltage of any of the ICs it is directly connected to (or input signal that may have a reversed polarity of what is expected), then your circuit may be in trouble. The protection diodes and series resistor I mentioned then prevent any damage from happening.
Looking good.
One problem you might encounter is that in clocked digital logic, the data input usually needs to be stable for some time before the clock is applied. This is called the setup time, the Texas Instrument data sheet for the CD4076B specifies the minimum setup time as 80ns for a 10V power supply or 60ns for 15V (so about 70ns for 12V).
The OR gate implemented with the D3 to D5 diodes may or may not provide enough delay to satisfy this setup time requirement.
If you find that the flip-flops don’t always capture the correct value, it might be because the setup time is insufficient.
The TI data sheet allows for a fairly slow clock rise and fall times (up to 5µs for power supplies above 10V) so you could just slow the rising time to, say, around 200ns with a simple RC low pass filter between the point where all the cathodes of D3 to D5 meet and the clock inputs.
I’m not completely sure of the math, but I would start with capacitor and resistor values C and R such that RxC is about 100ns e.g. R=100 ohms and C=1nF. Or 10 ohms and 10nF since you already have 10nF capacitors in your circuit.
Edit: You actually might need to beef up your input 10nF capacitors so that the generated pulse is long enough to not get completely filtered out by the additional RC low pass filter.
Why is this pulse generating circuit necessary? Do you fear that one trigger might still be present on one input when a new trigger arrives on another input?
Thanks for the detailed remarks! I’ll keep that in mind when testing the circuit.
Exactly. The gate to trigger-converter is supposed to make the module more flexible in regards to what kind of signals it accepts. I was thinking, that e.g. clock dividers would make a good input source, but they typically output longer gate signals
Quick update: I’ve built a prototype on stripboard and it works pretty well already. There are some flaws, e.g. sometimes triggers are ignored and the channels don’t switch accordingly. The circuit definitely needs some improvement and further testing under different conditions but the basic idea checks out. Will keep you updated!
In the video the prototype receives triggers from my grids sequencer and sends CV (via a quantizer) to the V/Oct input of a synth voice in drone mode
