Both Vgs(off) (gate voltage when JFET is fully off) and Idss (max current when Vgs = 0) differ, but if that’s an issue depends on the circuit, and JFETs aren’t very precise devices in the first place (both these parameters have fairly wide ranges). As I mention here about two somewhat similar JFETs, “if there’s no trimming procedure odds are the circuit is fine with either (or the designer just tested one, and you’re kind of screwed anyway).”
