The board is looking good!
As in, better than stuff you’d find behind the panel of commercial releases, for sure. We’re trying to workshop it to perfection, but with it passing the DRC, I’m confident it works.
For grid alignement, electronics being a cursed mix of international units, i favor local alignement over having a strict grid.
On routing, automating it is hard, and the adage says “never trust the autorouter”. It’s like the game of go, it engages human aesthetics and heuristics too much to brute force, though maybe modern ML tech might change this in the future. Routing is easy if the layout is good anyway… And the computer certainly can’t do autolayout!
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Thank you for saying that!
It means a lot, because I really have no reference to judge it against.
The plugin’s (automatic) version seems cleaner, but it has a ton of DRC violations.
I will try to fix those and see what I end up with.
I don’t think the autorouter did a great job honestly, let alone a better one haha. But either case, you really should try to figure out a way to align the pots… I’m sure something can be moved out of the way to make it work.
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Are the two electrolytic caps the 10uF (or whatever) bypass caps? They would better be placed close to the power header. I don’t see any 100 nF bypass caps near the chips.
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Yes, I tried to fix it but every change that I make bumps the error counts up by 20 more, ha ha.
Is there an easy way to align objects? What I did so far was measuring with the ruler and placing according to that.
Click the object to align, click the reference, align tu horizontal center.
There’s also the solution of setting position numbers manually - most fields like shif-m move support math equations
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I guess so…? sigh guess it’s time to move stuff around again.
They are near the TL074, at the top
For the 100nf bypass, physical proximity is very important, even a few centimeters reduce their effect on stabilizing the power supply, hence why he suggested moving the pair effecting the bottom chip closer.
For the 10µF it doesn’t matter as much
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Still, at the other end of the board from the header is a bit much.
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I have rearranged the board so that now the caps are much closer to the TL074.
I also replaced the ‘Thonkiconn’ footprint to the ones you have in your repository. (Thank you for offering that)
The new footprint has more rigid courtyard requirements, so I have to ignore some of the DRC errors regarding that, as it seems fine in the 3d simulation.
I did notice that after replacing the footprint, the connections from the audio jack pads to the respective components were lost, so now the audio jacks are disconnected. Is there a way to restore the connections and also, in the future to replace footprints while retaining the connections? I have tried to update from the schematic but all it does is revert the PCB to an older iteration.
You still have the TL072’s bypass caps (100 nF) up next to the TL074, which is not where they should be. They’re pretty useless sitting next to the TL074’s bypass caps.
The routing still looks a lot more complex than I’d think necessary, with an awful lot of vias. Just curious, in the last schematic I see the input and output op amps are the TL072 and the rest are TL074. Is that still the case? It might have worked out better to have the TL072 be the saturation and output. Being close together in the schematic it makes sense for them to be the same chip in the layout.
Another thing I belatedly notice is that it looks like all your traces are the same width. My usual practice is to use 0.25 mm for most signals and 0.75 mm for power rails, or anything likely to carry relatively large current. 0.25 mm might be okay but I prefer wider for power.
I don’t understand your question about the jacks. If the pads are in a different position, then the traces you drew to the pads will no longer connect. You need to delete the old traces and draw new ones. KiCad will not automatically change your routing for you.
I really don’t understand this.
Thanks for taking another look!
You are correct about the TL072 taking care of the in+output.
Just so I know for sure, which one of those is responsible for saturation, U2B or U2D ?
I’ll re-work it as you suggested and fix the bypass caps for the TL072.
Regarding the tracing, I’m following Aria’s advice on going lateral on one side and vertical on the other, which helps quite a bit. Do you have any other suggestions or guidelines?
I did try to have the +12 and -12 trails at 0.5mm, but couldn’t do so for GND, as I ran out of space. Eurorack is less forgiving in that sense…
Regarding the jacks, it was a Kicad error, it doesn’t like when I use Save As, because it somehow disconnects between the schematic and PCB editor. I solved it by saving the schematic as a new file, thus creating a new project.
U2D
Again, you really should not need ground traces.
The way to change a footprint is to go into the schematic editor window, click on the component in question, and change the footprint for that component. When you do so the existing connections are unchanged and apply to the new footprint. The new footprints and (if the pad positions are different) the ratsnest lines will be present in the PCB layout once you update that from the schematic.
I don’t know what you did but it must have been something else.
I have no idea what happened here but I suspect you made some mistake.
You should just be able to change the footprint as mentioned above. If you wanted to save the version with the original footprint first you could do that in the main KiCad window with Save As; that will create a new project that is a copy of the current one and open it. You could make your changes in that new project, or switch back to the original project and make changes there. In any case there should be no undoing of your work. If you think that is what you did do and got an unexpected result, try to replicate the problem; if you can do so, then open an issue on the KiCad Gitlab.
(DON’T use Save A Copy in the PCB editor, that just saves a copy of the PCB that is not linked to the schematic.)
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I think it’s just as you’ve explained, I will Save As at the project window from now on, instead of saving the PCB.
Could you really avoid ground traces? I’m assuming that you use the ground pour, but in such a crammed design, I’m “losing” the ground pour very quickly. It’s just a matter of experience I guess.
I don’t know. I don’t design such narrow, densely packed boards. It may be that for a board this size you really should use SMD.
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I just designed one like this today - for the love of the sport, I arranged many components by value & aesthetics rather than numerically
i ended up with 252 vias lol. This way i never had to connect a ground manually. i bet it will work just fine. the traces are 0.25mm, twice what they can handle.
A gratuitous fancy view:
Big the Cat for scale
Jlc’s human reviewer accepted my board within 30 seconds of it being sent. (that’s their normal review speed during chinese office hours btw, always within minutes)
in general, if you design boards to the default values kicad ships with, and don’t do anything weird, jlc can build it just fine.
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Wow, looks like a fun project.
Plus, it makes me feel a bit better for placing so many vias.
Thanks for all your help so far.
The board has been rearranged: caps are all in place and OpAmps reassigned.
I have 5 more “Thermal relief connection to zone incomplete” erros, can I ignore those or should I resolve them? (and if so, what is the easiest method of doing so?)
I always ignore them 
Kicad insists on ground connections having two spokes for thermal reasons, but unless the component is carrying a lot of current, it doesn’t matter - and KiCad doesn’t know that.
(If your project is about ready, you should upload a zip so we can give it a proper look with the editor)
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