Hey guys! I need to build a clock divider but every research I make confuse me a lot but I finaly made a circuit I don’t know if it’s good or not?
Here is the main part of it, don’t know if it needs more components, like inverters because the CD4520 changes its output on rising edges so I don’t get why people uses inverters and AND logic gates 
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The CD4520 has a clock input that responds to a LOW to HIGH transition and one that responds to a HIGH to LOW transition, so you can choose whichever fits your purpose best. Have a look at the truth table in the datasheet how to use either one of the clock inputs.
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Here is it! Yeah it changes on rising edge which make more sense, well anyway thank you ^^
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I think I talked about binary ripple carry counter for a different application, but I wonder if the 4040 would work for your project.
It would give you more stages from the look of things.
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Notice that you always need to use both clock inputs. One of them will get the clock pulse while the other determines whether the former is enabled or not.
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Never looked at cd4520, interesting. I know like the fonik and ronnberg designs use cd4069 inverters because the divided outputs coming straight out of a 4024 is inverted. So without the inverter, the divided outputs would be on/high until triggered, which would be pretty weird to use
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Oh like I have to send cock to both modules? Or to the chip enable pin? I don’t get what you want to mean sorry
You have to use one of the CD4520 pins to enable the other — two pins are labeled CLOCK and ENABLE (to increment on rising edge) but they are equally well ENABLE and CLOCK (incrementing on falling edge). In your schematic ENABLE is tied to +12 V, so it’s taken care of.
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Okay yeah! I followed the datasheet ^^ thank you for your explanation.
I’m just kinda bad in English sorry! 
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The first and second row of the table explain how each of the 2 counters in the chip responds to signals. In the table shown in the picture below you see that the inputs on pin 1 and 2 (and on 9 and 10 for the 2nd counter) are called CK0 (clock0) and ĈK1 (^clock1), so different than in your table, but they have the same function. Also have a look at the diagram to the right, you can see there that both CK0 and ĈK1 are part of the driving mechanism of the counter.
The first line in the table explains that if you put a signal (most times that will be a square wave) with a rising edge on the clock input CK0 and an 1 on the ĈK1 input then the counter will be incremented on every rising edge of the CK0 signal.
The second line explains that if you put a 0 at the clock input CK0 and a signal with a falling edge on the ĈK1 input, then the counter will be incremented on every falling edge of the ĈK1 signal.
All other combinations of signals on the clock inputs will not change the counter’s state.
Note that the reset signal must be at 0 Volts for the counter to count.
If you have more questions, don’t hesitate to ask! 
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Ooh okay! But your pinout shows clk0 and člk1 mine was showing clk and enable so yeah I got a bit confused but now I understand ^^ it’s just both signals going into an and gate and going into the clock of the binary counter.
Well thank you a lot now I completely understand the truth table
The only problem that I got was: do I have to put resistors to the signals? Pull-down resistors? Buffers? Things I didn’t see on the datasheet
Anyway, big thanks for helping me! 
There’s a discussion here of a 4520 based clock divider, with the working version shown here:
The input clock and reset signals are buffered with a transistor, which inverts them, and then they’re re-inverted with an inverter IC. Then the outputs are inverted before being ANDed with the clock to make the long outputs into short clock pulses.
There must be ways to reduce the number of inversions. For instance the inputs could be buffered with voltage followers which would eliminate the need to re-invert them. Or why not use the falling edge clock inputs instead of the rising edge ones?
The output inverters are used so that for instance the /2 output doesn’t turn on until the 2nd clock pulse after a reset, the /4 output doesn’t turn on until the 4th pulse after, and so on. Could a NAND instead of AND eliminate the need for them? (Maybe not. Too soon after waking up to work it out.)
This circuit uses both sides of the 4520 to do up to /256, if you only need up to /16 you could omit the bottom half.
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This depends on the source of your clock signal, not so much on the CD4520. In general in a ‘logic’ circuit you do not need to use resistors or other components to interconnect logic building blocks if all building blocks use the same power supply voltage. You can simply interconnect them with a wire. What is your clock source?
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Woaw that’s pretty complicated! I kinda understand the circuit like every block but I don’t get why it would be useful to invert and re-invert all the clock signal mmh… Is that only to get short pulses? Else you could just use a RC circuit to get them?
And yeah to me things happens on the rising edge of the clock signals on euroracks modular synth so it seems logic to me to change the states of the divided output on rising edge rather than falling edge
The cock signal comes from whatever with a maximum voltage of 12V I guess. I just added a 1N4148 diode at the jack input to prevent reverse polarity but otherwise okay thank you. ^^
The circuitry following the CD4050 is ‘some’ logical combination of the outputs of the two 4050s some of which leads to a logical 1 to appear at the outputs for a short or a longer number of input pulses. I wouldn’t worry about that example.
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The idea is that the designer wants all clock divisions to start with a “tick” when a reset is done. Without the inverters every division would be off, then /2 would be on for subsequent pulses 1, 3, 5, 7…; /4 would be on for pulses 3, 7, 11, 15…; /8 would be on for pulses 7, 15, 22, 31… and so on. With the inverters /2 is on at reset and for subsequent pulses 2, 4, 6, 8…; /4 is on at reset and for pulses 4, 8, 12, 16; /8 is on at reset and for pulses 8, 16, 24, 32… and so on. So it just means all the clocks start at reset rather than (effectively) one tick before reset.
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Wow okay well I don’t think I really need that so I’m just gonna stick with the easiest thing right now. But thanks for your explainaion, it makes moe sense now!
When you invert all the outputs of countup counter, you make a countdown counter. So probably a chip like this
https://www.ti.com/lit/ds/symlink/cd40193b.pdf
could serve instead of the 4025 + two quad inverters (except you’d need two to get down to /256, so only saving one chip). Probably!
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