I then built the design with the 1/1 output working (I’m pretty sure that’s a no-brainer anyway ), but the other outputs/timings are sporadic and really inconsistent, even though the speed of the input clock stays the same. So I am a little perplexed, if anyone is able to find any issues in the layout or the terrible picture attached, that would be a great help!
A trigger on the RST input will pulse the RESET pin on the 4024. The idea is that every output division will then reset, so they will all be ON with the next clock pulse (and then continue with 1/2, 1/4, 1/8 and so on from there).
What is the short red wire on the photo? I cannot see it on the schematic, and it seems illogical to me.
Are you sure no wires are touching (sometimes)? The white wire on the left (at the height of pin 1 of the IC 4024) seems to be stripped more than I would do; if this was done in other places, there might be a chance of wires touching.
Hi, yes, I have checked these connections specifically, they don’t appear to be touching anything else.
I’m wondering if there is a clock divider schematic/diagram more commonly followed by builders in the community, as they appear to be few and far between when I search for them!
I’ve found another diagram, however am still unsure as to whether it would help to build this one either - it has been sketched at double scale, meaning that there are some resistors and transistors in the diagram that appear to be placed between lines? (Hence the uncertainty on whether to build or not).
I can vouch for the Hagiwo 4040 clock divider! Really simple and elegant design. I have added transistors (2n3904 or similar) for the divided outputs to get the 9V output I wanted, which as a bonus also protects the chip from unwanted input signals.
Sorry should have made this one clear, that red wire doesn’t actually connect anywhere other than pin 1; it was a mistake during the build and apparently I never got around to removing it completely.
The supply doesn’t have to be limited to +5 V; the TC4040BP can take up to +20 V for power. If you use +12 V power you’d get about +12 V outputs.
But as you say the transistor buffers serve to protect the chip; they also boost the maximum output current, which from the chip is only about 1 mA. Which is probably enough for most purposes, but I’d add the buffers.
I’d also add a diode between the clock input transistor base and ground, to protect the transistor against reverse bias.
I’m puzzled by the reset input. I’d think a 100k to ground would be better than 10k. It probably should have a Schottky diode to ground (after a 1k series resistor), and especially if powering with +5 V another Schottky to the power rail or else just a 5.1 V Zener diode to ground, for chip protection. And I don’t understand the point of the series 10k. As you can see from the designs I’ve posted, most people use an RC network and transistors or op amps to shorten and condition the reset signal (and protect the chip), and sometimes to provide a reset button. The Rönnberg design has a puzzling looking bit that as I recall serves to generate a reset pulse immediately after powering up, to guarantee the divider is starting from a known state.
I have done a quick strip board draft of this schematic, please let me know of any errors. @analogoutput I tried to incorporate some of what you said above, however I am planning on powering it with 12V (coming in on the red line on the left of the diagram - GND is black and -12V blue even though it’s not used). I will admit I got lost near the end
P.S. I think I understood the transistor data sheet correctly but not 100%!
Thanks as always everyone, much appreciated!
), but the other outputs/timings are sporadic and really inconsistent, even though the speed of the input clock stays the same. So I am a little perplexed, if anyone is able to find any issues in the layout or the terrible picture attached, that would be a great help!
