I thought to use this
so i do this (between clock in and gate output)
please, @analogoutput , @Sonosus , @TimMJN … does that sound good to you ?
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I like how you summoned us like some sort of three horsemen. 
Anyway, this will not work right now, and if it does, it’ll have some undesirable properties. Starting with the latter, the LOW state of this gate will be 1 diode drop above ground, so 0.7V. That’ll mean that VCAs wont fully close, and ADSRs might not retrigger. Also, the output impedance of this gate will be pretty high, that might become a problem when using passive mults.
Then why it won’t work; this gate relies on the output being either pulled HIGH, or driven LOW through either of the diodes. In the sequencer schematic you posted, the ‘gate’ bus is either driven HIGH through D11-D20, or left floating. This is already bad practice on its own, you should add a 10k pulldown to it. The problem is that this bus being pulled LOW cannot drive the gate LOW. The pulldown and pullup resistor will form a voltage divider, and the AND output will be left somewhere halfway. The same goes for the clock input, which should be considered high impedance and incapable of driving anything.
Either way, I’d suggest you slap in something like 4081. There’s some transistor designs which would work too, but assuming you want to do the same thing to the other ‘gate’ bus, you’ll be off quicker using an IC.
Hope that helps 
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Thanks !
honestly i dont think at this point add another IC.
My schem is not exactely the same as above, I combined several schems, and I only have one “bus gate” output, and I added a buffer
here’s mine
If it’s not possible with diodes I would leave it like this.
(the gate still works when I cut steps)
I will already add a pulldown resitance as you advised and see what I do with it all.
i don’t understand, there is a difference between AND diode and CD4081 ?
From what I gather here, most of wait I said earlier still applies to this version. A buffer on the gate line is a big improvement, this definitely requires the pulldown resistor before it. You could get the passive AND working if you take the gate behind the trigger, and the clock behind the gate>trigger converter.
One is a passive device with all included quirks, the other is a nicely behaved active device. The biggest downside for me would be the 0.7V LOW state…
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i add the gate to trigger circuit, i’m not sure if i need to keep the gate out buffer.
and the pulldown resistor now is already in the circuit
something like this ? what do you think ?
I must compliment your MS paint skills
I don’t think you need a second gate-to-trigger converter, as you already have to one on your clock input setting the trigger length. Instead, I’d add another buffer. Prepare for powerpoint art:
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Think that’ll work!
20 chars
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thx 
is it the good place for the pulldown resistor i’ve add (does he need others ?), and which value plz,100 ohm ?
it’s the right place yes, and I’d go 10k
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thanks a lot @TimMJN , i will try this tomorow
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yeah its a very simple and great solution; it use less place than the cmos chip, good idea !
Tell me if it working please
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here a AND logic version with transistor, but I tkink that this look more boring than the cmos chip… or maybe just use a little part of the circuit ?..
do you know why the passiv method didn’t work ?? I think that 4081 is the best solution… (but not the most laziest)
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thx
of course, no problem
wait for me to test it 
before :
yes no problem 
YEEEEES !!!
i made the modification and tested the gate out with an Envelope gen and it’s cool, all works fine
thx again @TimMJN
@saint_et_moudulard now i can say that the passive way with diode work
btw i think it 's not a real passive AND circuit, because it need +12V with the 100K to the diode …), a passive circuit don’t need V at all.
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Looking forward to seeing all in the verified stripboard thread… Please
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OK tip top !! I write this tip on my list for my future sequencer, thank you !! 
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i’m on the DIYLC at this time, very very soon
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how value have you used for the pull-up resistor ?
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100k
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