Routing 'pitfalls' in EasyEda

I was working on a project and had a PCB made by JLCPCB. I had designed the pcb using EasyEda.

This is part of the schematic.

While checking the circuit I noticed that there was no copper between U1.1 pin4 and U5.1 pin 2, nor was there a connection from U1.1 pin 4 to either R6 and R7.
R6 and R7 were connected nicely to U5.1 pin 2. Looking at the diagram I had drawn there should be one, shouldn’t it?

The thing is, that the red dot on the wire between R7 and U5.1. pin 2 suggests that there is a connection from that wire to the wire connected to U1.1 pin 4. But if you click on the connecting wire (highlighted in red), you can see that the connection does not go beyond the red dot.

Only after redrawing the connecting wire from the connection point of U1.1 pin 4 to the connection point of U5.1 pin 2,

clicking the schematic shows (again highlighted in red), that now there is a connection between U1.1 p4 and U5.1 p2. Consequently I could update the pcb and add the missing copper track.

So the lesson to learn here is that one should always connect a wire from an electronical component to another component and be very careful with connecting one wire to another wire.

It is a bit odd that one can draw a connection between 2 wires and that this does not result in an actual connection, but maybe there is a use case where this makes sense / or this is a bug.

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Think I may have had that once in KiCad. But normally it works.

Sounds like a bug to me. I don’t use EasyEDA, but in KiCad when there are two traces supposedly connected like that, it draws a junction marker.

(Nonsensical schematic loosely based on OP’s)

You can manually remove that junction marker

but it explicitly marks that point with an open square signifying an unconnected trace, and more to the point, when you run ERC it fails:

image

Glancing at the EasyEDA documentation I see it does provide DRC for layout errors but does not seem to have ERC for connection errors. If so then it’s up to you to spot them and if indeed you can have two disconnected tracks that visually are indistinguishable from connected ones then that’s a serious bug or misfeature in the EDA.

Added: If I add a component for U1C pin 8 to connect to then there are no ERC violations, which surprises me

but still, the disconnected point marker is there.

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I’ve noticed when I used easy eda, you do have to be careful how you place your connection in scheme to make sure it’s actually connected.

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